Re: [libre-riscv-dev] [OpenPOWER-HDL-Cores] microwatt decoder tables: M-Form and X-Form switched RS and RB

[Paul Mackerras <paulus@ozlabs.org>]

Hi Luke,

On Mon, Jun 01, 2020 at 01:20:45PM +0100, Luke Kenneth Casson Leighton wrote:
> anton, paul, and team, hi,
> 
> we noticed that in microwatt decode1.vhdl tables, M-Form has:
> 
> * op1 is RA
> * op2 is a constant or RB, which is in the *3rd* field (M-Form) position
> * op3 is RS, which is in the *second* Form position
> 
> where in X-Form it is:
> 
> * op1 is RA
> * op2 is a constant or RB, where RB is from the *2nd* field
> * op3 is RS (or RC), which is in the 3rd position.

I'm not quite following, sorry.  When you talk about the second or
third position or field, are you talking about where they are in the
instruction word (and if so, are you counting left to right, or right
to left), or are you talking about the input_reg_a/b/c entries in
microwatt's decode tables?

If you're talking about positions in the instruction word, then either
I'm misunderstanding your paragraph about X-form above, or it is
incorrect, because instructions such as "and" and "or" take their
inputs from RS and RB, so op1 is not RA for them, though it is for the
arithmetic instructions.

(I asked some of the original Power architects why there was this
nonuniformity in the Power ISA where rotate and logical instructions
use RS and RB as their inputs, whereas arithmetic instructions use RA
and RB as inputs.  The answer was that in the Power1 implementation,
they were very short of gates, so they made the logic for rotating and
masking data for store instructions also serve as the logic for doing
the rotate and mask instructions.  Since stores take their data from
RS, that meant that the rotate and shift instructions also took the
data to be rotated or shifted from RS.)

Regards,
Paul.

_______________________________________________
libre-riscv-dev mailing list
libre-riscv-dev@lists.libre-riscv.org
http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev