From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
To: openpower-hdl-cores@mailinglist.openpowerfoundation.org
Cc: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: [libre-riscv-dev] microwatt decoder tables: M-Form and X-Form switched RS and RB
Date: Mon, 1 Jun 2020 13:20:45 +0100
Message-ID: <CAPweEDz9S=HXwnZqiQ9YtsiseGw6Do5qJnPE9kCjSjmozTWqVQ@mail.gmail.com> (raw)
anton, paul, and team, hi,
we noticed that in microwatt decode1.vhdl tables, M-Form has:
* op1 is RA
* op2 is a constant or RB, which is in the *3rd* field (M-Form) position
* op3 is RS, which is in the *second* Form position
where in X-Form it is:
* op1 is RA
* op2 is a constant or RB, where RB is from the *2nd* field
* op3 is RS (or RC), which is in the 3rd position.
so decode1.vhdl has this, for rldcl:
0b1000,SHIFT_ROT,OP_RLCL,NONE,RB,RS,RA
we're going to flip that to:
0b1000,SHIFT_ROT,OP_RLCL,NONE,RS,RB,RA
this will put the shift-rot pipeline "in line" with the arithmetic
(and logical) ones.
it *might* be the case that if you did the same thing, you would be
able to cut at least one pair of 64-bit MUXes from microwatt, because
RS and RB (2nd and 3rd operands) would no longer be
special-case-swapped for any Shift-Rot operations. i mention it
because microwatt is intended to be tiny.
best,
l.
---
crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
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Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-01 12:20 Luke Kenneth Casson Leighton [this message]
2020-06-01 23:13 ` [libre-riscv-dev] [OpenPOWER-HDL-Cores] " Paul Mackerras
2020-06-02 0:01 ` [libre-riscv-dev] " Luke Kenneth Casson Leighton
2020-06-02 12:10 ` Luke Kenneth Casson Leighton
2020-06-03 0:40 ` [libre-riscv-dev] [OpenPOWER-HDL-Cores] " Paul Mackerras
2020-06-03 1:28 ` Luke Kenneth Casson Leighton
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