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From: Yehowshua <yimmanuel3@gatech.edu>
To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: Re: [libre-riscv-dev] AMD ISAs
Date: Tue, 9 Jun 2020 19:23:53 -0400
Message-ID: <30C067F4-4E6C-498D-A76F-4C793EE36E4D@gatech.edu> (raw)
In-Reply-To: <CAPweEDxzzWyAo5s2tM=-MuBkQ7FBBC1_Br-z9m2ON-x=E3p-6g@mail.gmail.com>



> On Jun 9, 2020, at 7:21 PM, Luke Kenneth Casson Leighton <lkcl@lkcl.net> wrote:
> 
> in addition, we need to consider that the level of instruction
> compression (which reduces shared L1 I-Cache usage) anticipated
> through the hardware-level compression in SimpleV will be completely
> unobtainable for AMDGPU ISA interoperability... because we will be
> forced *to* have AMDGPU ISA interoperability.

This is a valid point.
I’ll get back to you on this.
I feel like there is a good way to do this...

Yehowshua
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Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-06-09 23:15 Yehowshua
2020-06-09 23:16 ` Yehowshua
2020-06-09 23:18   ` Yehowshua
2020-06-09 23:25   ` Jacob Lifshay
2020-06-10  0:59     ` Yehowshua
2020-06-10 11:28       ` Luke Kenneth Casson Leighton
2020-06-09 23:21 ` Luke Kenneth Casson Leighton
2020-06-09 23:23   ` Yehowshua [this message]

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