From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: Re: [libre-riscv-dev] AMD ISAs
Date: Wed, 10 Jun 2020 00:21:27 +0100
Message-ID: <CAPweEDxzzWyAo5s2tM=-MuBkQ7FBBC1_Br-z9m2ON-x=E3p-6g@mail.gmail.com> (raw)
In-Reply-To: <1448919C-8B02-48C8-9B0D-9C03C64E1765@gatech.edu>
On Wed, Jun 10, 2020 at 12:15 AM Yehowshua <yimmanuel3@gatech.edu> wrote:
>
> All of AMDs ISA are open here.
> https://gpuopen.com/documentation/amd-isa-documentation/ <https://gpuopen.com/documentation/amd-isa-documentation/>
>
> It may be worthwhile trying to make our GPU “appear” to be an AMD device.
the problem with doing so is that the processor effectively becomes
"Dual ISA". everyone that we've talked to with significant experience
in processor design has raised eyebrows at the complexity involved in
a dual-ISA design.
it is not an insurmountable issue: it just should in no way be
underestimated, for the trade-off of not having to write any kinds of
drivers.
in addition, we need to consider that the level of instruction
compression (which reduces shared L1 I-Cache usage) anticipated
through the hardware-level compression in SimpleV will be completely
unobtainable for AMDGPU ISA interoperability... because we will be
forced *to* have AMDGPU ISA interoperability.
l.
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Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-09 23:15 Yehowshua
2020-06-09 23:16 ` Yehowshua
2020-06-09 23:18 ` Yehowshua
2020-06-09 23:25 ` Jacob Lifshay
2020-06-10 0:59 ` Yehowshua
2020-06-10 11:28 ` Luke Kenneth Casson Leighton
2020-06-09 23:21 ` Luke Kenneth Casson Leighton [this message]
2020-06-09 23:23 ` Yehowshua
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