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From: Yehowshua <yimmanuel3@gatech.edu>
To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: [libre-riscv-dev] Yehowshua Tasks
Date: Mon, 15 Jun 2020 18:47:27 -0400
Message-ID: <338F2BAA-7632-49AD-9769-12ECF1B52F84@gatech.edu> (raw)

Hello again Luke,

	As I wrap up my thesis, I’d like to get into the flow of things more.
	I can put I about four hours a day on LibreSOC.

	1. What are some tasks I can get started with right away?
	Mainly related to nMigen - I don’t have patience for QEMU 
	right now. Last time I did extensive QEMU work was a pretty
	painful experience about a year ago.

	2. I can go ahead and write a bench test for Minerva’s cache.

	3. Also, how can I get more familiar with the LD/ST comp unit
	including the dual cache even/odd architecture from the YouTube 
	video you linked to earlier today?
	Is it related to the memory Hierarchy section in Mitch Alsup’s 
	computer architecture chapter 10?

Yehowshua
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Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-06-15 22:47 Yehowshua [this message]
2020-06-15 23:55 ` Luke Kenneth Casson Leighton
2020-06-16 11:58   ` Luke Kenneth Casson Leighton
2020-06-16 13:50     ` Yehowshua
2020-06-16 14:35       ` Luke Kenneth Casson Leighton

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