From: Yehowshua <yimmanuel3@gatech.edu>
To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: Re: [libre-riscv-dev] Yehowshua Tasks
Date: Tue, 16 Jun 2020 09:50:30 -0400
Message-ID: <A49F3570-7103-4FF2-BD60-7896CA427FFC@gatech.edu> (raw)
In-Reply-To: <CAPweEDyaGajktrgnr_d=X8zgbTuJukRc1uuXnxrkWqGkr53ieg@mail.gmail.com>
>
> it is *not* ok to have phase 1 proceed, the notification go back, "yes
> there is room in the cache for you" followed in phase 2 "actually i lied,
> we need to raise an exception now”.
Right. So I read through the Minerva cache and understand about
98% of it. There is a cache miss signal. And also a bus error signal
for example, if the cache tries to flush to the main memory via the
wishbone bus and it fails, it will raise bus_err.
What is the difference between hold off and go die?
I’m trying to write a simple unit bench for minerva L1Cache today.
Is there an NLNet task covering this?
Yehowshua
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Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-15 22:47 Yehowshua
2020-06-15 23:55 ` Luke Kenneth Casson Leighton
2020-06-16 11:58 ` Luke Kenneth Casson Leighton
2020-06-16 13:50 ` Yehowshua [this message]
2020-06-16 14:35 ` Luke Kenneth Casson Leighton
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