[libre-riscv-dev] [Bug 198] Formal correctness proofs are needed for low-level libraries in LibreSOC
2020-05-15 14:16 UTC (2+ messages) - mbox.gz / Atom
[libre-riscv-dev] [Bug 312] New: Formal Correctness Proof for CountZero needed (basically PriorityEncoder)
2020-05-15 14:16 UTC (4+ messages) - mbox.gz / Atom
` [libre-riscv-dev] [Bug 312] Formal Correctness Proof for CountZero needed (basically PriorityEncoder) "
[libre-riscv-dev] [Bug 305] New: Create Pipelined ALU similar to alu_hier.py
2020-05-15 14:13 UTC (52+ messages) - mbox.gz / Atom
` [libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py "
[libre-riscv-dev] [Bug 311] New: countzero function for Logic Pipeline
2020-05-15 14:01 UTC (7+ messages) - mbox.gz / Atom
` [libre-riscv-dev] [Bug 311] countzero function for Logic Pipeline "
[libre-riscv-dev] marketnext online call, earlier today
2020-05-15 13:44 UTC - mbox.gz / Atom
[libre-riscv-dev] daily kan-ban update 15may2020
2020-05-15 12:05 UTC - mbox.gz / Atom
[libre-riscv-dev] daily kan-ban update 14may2020
2020-05-15 11:19 UTC (19+ messages) - mbox.gz / Atom
[libre-riscv-dev] quick write-up about microwatt and Libre-SOC HDL
2020-05-14 21:54 UTC (2+ messages) - mbox.gz / Atom
[libre-riscv-dev] virtual coffee openpower, in 50 minutes
2020-05-14 21:08 UTC - mbox.gz / Atom
[libre-riscv-dev] [Bug 310] New: Function Units to cover multiple tasks
2020-05-14 14:59 UTC (4+ messages) - mbox.gz / Atom
` [libre-riscv-dev] [Bug 310] Function Units to cover multiple tasks "
[libre-riscv-dev] popcount and parity
2020-05-13 22:20 UTC - mbox.gz / Atom
[libre-riscv-dev] daily kan-ban update 13may2020
2020-05-13 22:02 UTC (7+ messages) - mbox.gz / Atom
[libre-riscv-dev] daily kan-ban update 12may2020
2020-05-13 19:54 UTC (11+ messages) - mbox.gz / Atom
` [libre-riscv-dev] teaching the benefits of using nmigen over VHDL/Verilog
[libre-riscv-dev] note on memory operation requirements for linux
2020-05-13 18:41 UTC (3+ messages) - mbox.gz / Atom
[libre-riscv-dev] [Bug 291] New: HDL Workflow and Coriolis2 chroot automated setup scripts
2020-05-13 17:58 UTC (9+ messages) - mbox.gz / Atom
` [libre-riscv-dev] [Bug 291] HDL Workflow and Coriolis2 chroot automated setup scripts "
[libre-riscv-dev] [Bug 309] New: investigate OpenTITAN
2020-05-13 17:27 UTC (4+ messages) - mbox.gz / Atom
` [libre-riscv-dev] [Bug 309] investigate OpenTITAN "
[libre-riscv-dev] [Bug 308] New: POWER variable-length encoding scheme needed
2020-05-13 9:38 UTC (2+ messages) - mbox.gz / Atom
` [libre-riscv-dev] [Bug 308] POWER variable-length encoding scheme needed "
[libre-riscv-dev] [Bug 238] POWER Compressed Formal Standard writeup
2020-05-13 9:38 UTC - mbox.gz / Atom
[libre-riscv-dev] little-endian only power cores and spec compliance
2020-05-13 9:11 UTC (10+ messages) - mbox.gz / Atom
` [libre-riscv-dev] [OpenPOWER-HDL-Cores] little-endian only power cores and spec compliance "
[libre-riscv-dev] more compatible alternative to BE instructions on LE processor
2020-05-13 8:17 UTC (4+ messages) - mbox.gz / Atom
[libre-riscv-dev] [Bug 307] New: look at installing a kan-ban board on top of bugzilla
2020-05-12 22:03 UTC (7+ messages) - mbox.gz / Atom
` [libre-riscv-dev] [Bug 307] look at installing a kan-ban board on top of bugzilla "
[libre-riscv-dev] PowerISA 3.1 (Power10) spec released
2020-05-12 15:56 UTC (20+ messages) - mbox.gz / Atom
[libre-riscv-dev] [Bug 304] New: Define minimum viable interface set for 180nm ASIC
2020-05-12 12:14 UTC (4+ messages) - mbox.gz / Atom
` [libre-riscv-dev] [Bug 304] Define minimum viable interface set for 180nm ASIC "
[libre-riscv-dev] [Bug 303] New: define peripheral set for 180nm ASIC
2020-05-12 12:12 UTC (4+ messages) - mbox.gz / Atom
` [libre-riscv-dev] [Bug 303] define peripheral set for 180nm ASIC "
[libre-riscv-dev] daily kan-ban update 11may2020
2020-05-12 10:06 UTC (3+ messages) - mbox.gz / Atom
[libre-riscv-dev] learning from a failed business
2020-05-12 8:11 UTC (2+ messages) - mbox.gz / Atom
[libre-riscv-dev] ppc-dev linux patch support for microwatt!
2020-05-12 3:29 UTC (12+ messages) - mbox.gz / Atom
` [libre-riscv-dev] Power memory fences and icache handling
[libre-riscv-dev] [Bug 70] evaluate Bus Architectures
2020-05-11 21:20 UTC (2+ messages) - mbox.gz / Atom
[libre-riscv-dev] [Bug 306] New: Formal Correctness Proof for ALU pipeline
2020-05-10 13:46 UTC (6+ messages) - mbox.gz / Atom
` [libre-riscv-dev] [Bug 306] Formal Correctness Proof for ALU pipeline "
[libre-riscv-dev] Handling Interrupts
2020-05-09 19:42 UTC (2+ messages) - mbox.gz / Atom
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