[libre-riscv-dev] [Bug 308] New: POWER variable-length encoding scheme needed

[libre-riscv-dev] [Bug 308] New: POWER variable-length encoding scheme needed

[bugzilla-daemon]

https://bugs.libre-soc.org/show_bug.cgi?id=308

            Bug ID: 308
           Summary: POWER variable-length encoding scheme needed
           Product: Libre-SOC's first SoC
           Version: unspecified
          Hardware: PC
                OS: Linux
            Status: CONFIRMED
          Severity: enhancement
          Priority: ---
         Component: Specification
          Assignee: lkcl@lkcl.net
          Reporter: lkcl@lkcl.net
                CC: libre-riscv-dev@lists.libre-riscv.org
   NLnet milestone: ---

instruction stream order needs to be sorted out so that the proposed
Compressed/48/64/VBLOCK encoding will fit.  currently, LE on POWER
is wholly unsuited to variable-length ISA encoding due to the opcode
being at the wrong end of a sequential instruction byte stream

https://libre-soc.org/openpower/

http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-May/006553.html

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[libre-riscv-dev] [Bug 308] POWER variable-length encoding scheme needed

[bugzilla-daemon]

https://bugs.libre-soc.org/show_bug.cgi?id=308

Luke Kenneth Casson Leighton <lkcl@lkcl.net> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
           See Also|                            |https://bugs.libre-soc.org/
                   |                            |show_bug.cgi?id=238
    NLnet milestone|---                         |NLNet.2019.10.Standards

--- Comment #1 from Luke Kenneth Casson Leighton <lkcl@lkcl.net> ---
note, not to be confused with bug #238 which is *actual* compressed
(16-bit) instruction encodings.

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