From: Jacob Lifshay <programmerjake@gmail.com>
To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: [libre-riscv-dev] daily kan-ban update 17jul2020
Date: Fri, 17 Jul 2020 20:27:20 -0700
Message-ID: <CAC2bXD4j+1QqJQ54k_6jysjj9ppeQkKyw79sGcaN7EUSnvAUbA@mail.gmail.com> (raw)
today:
started adding fsm div
got a test where a whole bunch of the core fsm transition functions
are strung together combinatorially to work
(soc.fu.div.test.test_fsm.TestDivState.test_div_state_comb), so that
means that the soc.fu.div.fsm.DivState* classes all work.
However, when I try to wire them up in a simple synchronous fsm
(soc.fu.div.test.test_fsm.TestDivState.test_div_state_fsm), it doesn't
seem to work: I think the simulation process I made that checks
outputs is somehow getting desynchronized from the process that
toggles inputs -- I added some extra wires that the check process
toggles. it appears to me as though the check process is somehow
delayed an entire divide operation (8 or 9 cycles, since I'm testing
an 8-bit divider to make it easier).
Will try to fix that after tomorrow
Jacob
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Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-18 3:27 Jacob Lifshay [this message]
2020-07-18 3:37 ` Luke Kenneth Casson Leighton
2020-07-19 7:04 ` Jacob Lifshay
2020-07-19 11:13 ` Luke Kenneth Casson Leighton
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