From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: Re: [libre-riscv-dev] daily kan-ban update 17jul2020
Date: Sun, 19 Jul 2020 12:13:54 +0100
Message-ID: <CAPweEDxZbUfnpow3=bwGRRKOCpgi3UW-34DNzbyfZhxSqH6j6A@mail.gmail.com> (raw)
In-Reply-To: <CAC2bXD74AW2e1p=9A5AmmD=bzDkBHR77wQ_ZoV1TbczPZ+434A@mail.gmail.com>
On Sun, Jul 19, 2020 at 8:04 AM Jacob Lifshay <programmerjake@gmail.com> wrote:
> > > However, when I try to wire them up in a simple synchronous fsm
> > > (soc.fu.div.test.test_fsm.TestDivState.test_div_state_fsm), it doesn't
> > > seem to work: I think the simulation process I made that checks
> > > outputs is somehow getting desynchronized from the process that
> > > toggles inputs -- I added some extra wires that the check process
> > > toggles.
> I'm specifically using Delay to delay a fraction of a clock cycle after
> each Tick before measuring values, so Settle shouldn't be necessary.
hmm don't know what to suggest, then, other than saying "nuts to the
lot of it" and cookie-cutting microwatt divider.vhdl - into a new
subdirectory :)
l.
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Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-18 3:27 Jacob Lifshay
2020-07-18 3:37 ` Luke Kenneth Casson Leighton
2020-07-19 7:04 ` Jacob Lifshay
2020-07-19 11:13 ` Luke Kenneth Casson Leighton [this message]
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