[libre-riscv-dev] sun opensparc t2

[libre-riscv-dev] sun opensparc t2

[Jacob Lifshay]

the opensparc t2 is open source under the GPLv2, seems like it might be a
useful reference.
it is a barrel processor, hence doesn't get very good single-threaded
performance.

Jacob
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Re: [libre-riscv-dev] sun opensparc t2

[Luke Kenneth Casson Leighton]

On Thu, Apr 30, 2020 at 11:50 PM Jacob Lifshay <programmerjake@gmail.com> wrote:

> the opensparc t2 is open source under the GPLv2, seems like it might be a
> useful reference.

really what we need, the immediate priorities are:

* the L0 cache/buffer
* a TLB (Radix) implementation to study (Paul Mackerras's microwatt
may be the first)
* a (long, important) discussion on how many ALU and LD/ST Comp Units to
  allocate, and how they should be connected to the register file(s).

these things stem from the requirements as a GPU/Hybrid OoO
multi-issue Vector-capable design with an augmented POWER front-end,
where we will run GNU/Linux OS workloads, and we're going for
single-core at the moment.  consequently there's unlikely to be much
we could use from it *right now*.

however looking at this:
http://fpga.ashishbanerjee.com/opensparc/t2-architecture

opensparc T2 apparently has some important characteristics which we
will need for the next version: L1 cache crossbar interconnect, and it
uses the opencores.org wishbone memory controller, which we should
definitely track down.

> it is a barrel processor, hence doesn't get very good single-threaded
> performance.

interesting...

l.

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