From: Jacob Lifshay <programmerjake@gmail.com>
To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: [libre-riscv-dev] note on memory operation requirements for linux
Date: Fri, 8 May 2020 12:15:25 -0700
Message-ID: <CAC2bXD5Ecj1X+HJs=Nu100gh1zUcYxX1=qz+jdbbB4K24COgrw@mail.gmail.com> (raw)
I haven't checked but I'm 99% sure that we will need to implement standard
Power atomics, fences, ll/sc (including 128-bit version), cache flushes,
and non-cacheable load/store operations if we want to support Linux on our
october test chip.
Jacob
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Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-08 19:15 Jacob Lifshay [this message]
2020-05-08 23:11 ` Luke Kenneth Casson Leighton
2020-05-13 18:41 ` Luke Kenneth Casson Leighton
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