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From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: Re: [libre-riscv-dev] note on memory operation requirements for linux
Date: Sat, 9 May 2020 00:11:26 +0100
Message-ID: <CAPweEDzS9kK2UQkLxwdBfQ-LahutQg2PPDUiSH2w+foO9MbxkQ@mail.gmail.com> (raw)
In-Reply-To: <CAC2bXD5Ecj1X+HJs=Nu100gh1zUcYxX1=qz+jdbbB4K24COgrw@mail.gmail.com>

On Fri, May 8, 2020 at 8:15 PM Jacob Lifshay <programmerjake@gmail.com> wrote:
>
> I haven't checked but I'm 99% sure that we will need to implement standard
> Power atomics, fences, ll/sc (including 128-bit version), cache flushes,
> and non-cacheable load/store operations if we want to support Linux on our
> october test chip.

added  to page.  good catch.

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Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-05-08 19:15 Jacob Lifshay
2020-05-08 23:11 ` Luke Kenneth Casson Leighton [this message]
2020-05-13 18:41   ` Luke Kenneth Casson Leighton

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