* [libre-riscv-dev] note on memory operation requirements for linux
@ 2020-05-08 19:15 Jacob Lifshay
2020-05-08 23:11 ` Luke Kenneth Casson Leighton
0 siblings, 1 reply; 3+ messages in thread
From: Jacob Lifshay @ 2020-05-08 19:15 UTC (permalink / raw)
To: Libre-RISCV General Development
I haven't checked but I'm 99% sure that we will need to implement standard
Power atomics, fences, ll/sc (including 128-bit version), cache flushes,
and non-cacheable load/store operations if we want to support Linux on our
october test chip.
Jacob
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* Re: [libre-riscv-dev] note on memory operation requirements for linux
2020-05-08 19:15 [libre-riscv-dev] note on memory operation requirements for linux Jacob Lifshay
@ 2020-05-08 23:11 ` Luke Kenneth Casson Leighton
2020-05-13 18:41 ` Luke Kenneth Casson Leighton
0 siblings, 1 reply; 3+ messages in thread
From: Luke Kenneth Casson Leighton @ 2020-05-08 23:11 UTC (permalink / raw)
To: Libre-RISCV General Development
On Fri, May 8, 2020 at 8:15 PM Jacob Lifshay <programmerjake@gmail.com> wrote:
>
> I haven't checked but I'm 99% sure that we will need to implement standard
> Power atomics, fences, ll/sc (including 128-bit version), cache flushes,
> and non-cacheable load/store operations if we want to support Linux on our
> october test chip.
added to page. good catch.
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* Re: [libre-riscv-dev] note on memory operation requirements for linux
2020-05-08 23:11 ` Luke Kenneth Casson Leighton
@ 2020-05-13 18:41 ` Luke Kenneth Casson Leighton
0 siblings, 0 replies; 3+ messages in thread
From: Luke Kenneth Casson Leighton @ 2020-05-13 18:41 UTC (permalink / raw)
To: Libre-RISCV General Development
On Sat, May 9, 2020 at 12:11 AM Luke Kenneth Casson Leighton
<lkcl@lkcl.net> wrote:
>
> On Fri, May 8, 2020 at 8:15 PM Jacob Lifshay <programmerjake@gmail.com> wrote:
> >
> > I haven't checked but I'm 99% sure that we will need to implement standard
> > Power atomics, fences, ll/sc (including 128-bit version), cache flushes,
> > and non-cacheable load/store operations if we want to support Linux on our
> > october test chip.
>
> added to page. good catch.
3.1B (POWER10) doc says that atomics and so on are optional. this is
good, although performance would suck.
l.
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2020-05-08 19:15 [libre-riscv-dev] note on memory operation requirements for linux Jacob Lifshay
2020-05-08 23:11 ` Luke Kenneth Casson Leighton
2020-05-13 18:41 ` Luke Kenneth Casson Leighton
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