From: Jacob Lifshay <programmerjake@gmail.com>
To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: Re: [libre-riscv-dev] LLHD: Rust is used to drive research in Hardware Design Languages
Date: Tue, 14 Apr 2020 16:43:38 -0700
Message-ID: <CAC2bXD5JajsQS3nJAoBjhr3x-MZokUBOWaQd27SbtMK5-TP1sg@mail.gmail.com> (raw)
In-Reply-To: <CAPweEDyjmV0mQES42dzvAdSi=hm83woZ9v3dEny5Cf97VkdZ+A@mail.gmail.com>
On Tue, Apr 14, 2020, 16:21 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
wrote:
> On Wednesday, April 15, 2020, Jacob Lifshay <programmerjake@gmail.com>
> wrote:
>
> > Found this very interesting paper on LLHD, a new IR for HDLs, in this
> > week's This Week in Rust:
> >
> > https://arxiv.org/pdf/2004.03494
> >
> > The website is:
> > http://llhd.io/
>
>
> aw not another one! and did they add it to yosys? if not it is
> unfortunately just a toy. yosys is the defacto standard gateway to FPGAs
> and ASIC synthesis
Created an issue for adding RTLIL support:
https://github.com/fabianschuiki/llhd/issues/116
Jacob
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Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-14 23:01 Jacob Lifshay
2020-04-14 23:21 ` Luke Kenneth Casson Leighton
2020-04-14 23:43 ` Jacob Lifshay [this message]
2020-04-14 23:49 ` Luke Kenneth Casson Leighton
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