* [libre-riscv-dev] sum-addressed decoder @ 2020-05-01 14:32 Jacob Lifshay 2020-05-01 19:09 ` Luke Kenneth Casson Leighton 0 siblings, 1 reply; 2+ messages in thread From: Jacob Lifshay @ 2020-05-01 14:32 UTC (permalink / raw) To: Libre-RISCV General Development I found this interesting idea: https://en.wikipedia.org/wiki/Sum-addressed_decoder The patents appear to have expired. Jacob _______________________________________________ libre-riscv-dev mailing list libre-riscv-dev@lists.libre-riscv.org http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev ^ permalink raw reply [flat|nested] 2+ messages in thread
* Re: [libre-riscv-dev] sum-addressed decoder 2020-05-01 14:32 [libre-riscv-dev] sum-addressed decoder Jacob Lifshay @ 2020-05-01 19:09 ` Luke Kenneth Casson Leighton 0 siblings, 0 replies; 2+ messages in thread From: Luke Kenneth Casson Leighton @ 2020-05-01 19:09 UTC (permalink / raw) To: Libre-RISCV General Development On Friday, May 1, 2020, Jacob Lifshay <programmerjake@gmail.com> wrote: > I found this interesting idea: > https://en.wikipedia.org/wiki/Sum-addressed_decoder > The patents appear to have expired. "If the reader feels that this was an inordinate amount of brain-twisting work for a three gate improvement in a multi-cycle critical path, then the reader has a better appreciation for the level to which modern CPUs are optimized." hilarious :) could you raise a bugreport for it, as a future enhancement? it would be good to look at this later l. -- --- crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68 _______________________________________________ libre-riscv-dev mailing list libre-riscv-dev@lists.libre-riscv.org http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev ^ permalink raw reply [flat|nested] 2+ messages in thread
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