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* [libre-riscv-dev] daily kan-ban update 05jun2020
@ 2020-06-05 18:53 Luke Kenneth Casson Leighton
  2020-06-05 21:57 ` Jacob Lifshay
  0 siblings, 1 reply; 5+ messages in thread
From: Luke Kenneth Casson Leighton @ 2020-06-05 18:53 UTC (permalink / raw)
  To: Libre-RISCV General Development

yesterday:

* got surprisingly far very quickly with the unit test for the simple
core.  all integer comparisons of the regfile work fine.
* worked with Cole on the TRAP pipeline. there is oddness in microwatt from
SPRs being passed through reg data lines, had to sort that out

today:

* slept for several hours. very long day yesterday.
* tried tracking down Condition Register discrepancies in the read/write
side to CR regfile. related to bit ordering.
* go over LDST buffer to be able to help Tobias.
* start thinking how to pull in LDSTCompUnit into the pipeline tests.




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-- links below jump to the message on this page --
2020-06-05 18:53 [libre-riscv-dev] daily kan-ban update 05jun2020 Luke Kenneth Casson Leighton
2020-06-05 21:57 ` Jacob Lifshay
2020-06-05 22:03   ` Luke Kenneth Casson Leighton
2020-06-06  0:03     ` Cole Poirier
2020-06-06  2:13       ` Luke Kenneth Casson Leighton

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