[libre-riscv-dev] daily kan-ban update 24may2020

[libre-riscv-dev] daily kan-ban update 24may2020

[Luke Kenneth Casson Leighton]

yesterday:

* morphed MultiCompUnit to use regspec API
* wrote a module that understands the regspec API and documented it
* created a stub DataMerger class for Tobias to implement
* helped Cesar prioritise tasks
* created soc.fu.compunits with help from Cole
* created some more issues to keep track of forward-planned upcoming work
* reviewed pipeline code
* noticed that we can add OP_MT/FMSR to OP_TRAP

this morning:

* updated the pipelines, tests and formal proofs to use Data for INT regs.
* put a bugracker link to everyone's assignments on their wik homepage

today:

* possibly create a series of register files (or at least the bugreport for it)
* plan some unit test infrastructure for soc.fu.compunits
* split out unit tests from all test_pipe_caller.py and look at using
it for testing soc.fu.compunits

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Re: [libre-riscv-dev] daily kan-ban update 24may2020

[Tobias Platen]

this evening:

I began working on the elaboratable function of the DataMerger class, which I still haven't commited yet.
If all bits in addr_array_i are zero the output will be zero too as nothing needs to be merged. 
I' now asking myself weather the interface is correct, and how the DataMerger is used. 

:addr_array_i: an NxN Array of Signals with bits set indicating address match
:data_i: an Nx Array of Records {data: 128 bit, byte_enable: 16 bit}
:data_o: an Output Record of same type {data: 128 bit, byte_enable: 16 bit}

-- 
Tobias Platen <libre-soc[at]platen-software[dot]de>

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Re: [libre-riscv-dev] daily kan-ban update 24may2020

[Luke Kenneth Casson Leighton]

On Sun, May 24, 2020 at 8:23 PM Tobias Platen
<libre-soc@platen-software.de> wrote:
>
> this evening:
>
> I began working on the elaboratable function of the DataMerger class,

i answered in #216.

l.

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