From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: [libre-riscv-dev] daily kan-ban update 13jul2020
Date: Sat, 13 Jun 2020 15:48:50 +0100
Message-ID: <CAPweEDwKJ9qDOpi_eeOn-OgRD87_B1feZBCdpM6Efckn9sVS6w@mail.gmail.com> (raw)
yesterday:
* investigated LDST memory byte order discrepancy.
* reviewed proposed 40/45nm ASIC and found its interfaces to be
unachievable (25GBit/s is not practical in 45nm)
the review occupied the entire day and consequently no code was written.
today:
continue investigating byte order particularly of simulator vs qemu in
order to be able to get it right for the hardware.
what i do not understand - what concerns me greatly - is that the simulator
appears to be storing data from the opposite (big) end of its 8 byte
granularity, computing shiftmasks based on subtracting from 8.
this would tend to suggest a hardcoded dependency on a 64 bit memory width
allocation.
however reviewing both microwatt and pearpc i find no evidence of that,
hence my concern.
l.
--
---
crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
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Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-13 14:48 Luke Kenneth Casson Leighton [this message]
2020-07-13 15:40 Luke Kenneth Casson Leighton
2020-07-13 18:36 ` Tobias Platen
2020-07-13 19:35 ` Jacob Lifshay
2020-07-13 19:47 ` Cole Poirier
2020-07-13 22:09 ` Luke Kenneth Casson Leighton
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