[libre-riscv-dev] daily kan-ban update 13jul2020

[libre-riscv-dev] daily kan-ban update 13jul2020

[Luke Kenneth Casson Leighton]

yesterday:

* investigated LDST memory byte order discrepancy.
* reviewed proposed 40/45nm ASIC and found its interfaces to be
unachievable (25GBit/s is not practical in 45nm)

the review occupied the entire day and consequently no code was written.

today:

continue investigating byte order particularly of simulator vs qemu in
order to be able to get it right for the hardware.

what i do not understand - what concerns me greatly - is that the simulator
appears to be storing data from the opposite (big) end of its 8 byte
granularity, computing shiftmasks based on subtracting from 8.

this would tend to suggest a hardcoded dependency on a 64 bit memory width
allocation.

however reviewing both microwatt and pearpc i find no evidence of that,
hence my concern.

l.



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Re: [libre-riscv-dev] daily kan-ban update 13jul2020

[Luke Kenneth Casson Leighton]

On Monday, July 13, 2020, Cole Poirier <colepoirier@gmail.com> wrote:

> :
>
> Continue working on updating the wiki documentation for setup of dev
> environments. Luke I plan on also working on the alliance and
> alliance-check-toolkit sections,


excellent.

 , so I will comment on 'Bug 291

> - HDL Workflow and Coriolis2 chroot automated setup scripts'
> <https://bugs.libre-soc.org/show_bug.cgi?id=291> with my questions.


good idea.


>
> Cole
>
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Re: [libre-riscv-dev] daily kan-ban update 13jul2020

[Cole Poirier]

Yesterday:

* Updated dev-env-setup/hdl-dev-repos script to correctly set up nmigen-soc
* Started working on bringing
https://libre-soc.org/HDL_workflow/coriolis2/ up to date with
dev-env/setup/coriolis2-chroot

Today:

Continue working on updating the wiki documentation for setup of dev
environments. Luke I plan on also working on the alliance and
alliance-check-toolkit sections, as well as creating a section for
documenting our soclayout workflow. As far as I can tell this isn't
documented on the wiki, and I think it's important to have it well
documented as we are now ramping up the layout work with JP. I've
mostly been able to iron out the bugs in that workflow, but I may need
some help with configuration parameters, so I will comment on 'Bug 291
- HDL Workflow and Coriolis2 chroot automated setup scripts'
<https://bugs.libre-soc.org/show_bug.cgi?id=291> with my questions.

Cole

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Re: [libre-riscv-dev] daily kan-ban update 13jul2020

[Jacob Lifshay]

On Mon, Jul 13, 2020, 11:36 Tobias Platen <libre-soc@platen-software.de>
wrote:

> today:
>
> I've updated the .gitlab-ci.yml as it is missing a dependency
> (nmigen-soc).
> I was able to run the test_microwatt.py and test_issuer without any errors.
>

make sure to use https://github.com/nmigen/nmigen-soc.git since that
recently fixed a dependency issue that was causing nmigen to be reverted to
nmigen 0.1 from PyPI

>
> @programmerjake the .gitlab-ci.yml says
> https://github.com/nmigen/nmigen.git, is this correct.
>

yes, that is correct.

> First I tried out https://github.com/nmigen/nmigen.git which says
> nmigen-0.1 then
>
it's actually on nmigen-0.3-dev, you might have seen 0.1 from the
nmigen-soc dependency issue

Jacob
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Re: [libre-riscv-dev] daily kan-ban update 13jul2020

[Tobias Platen]

today:

I've updated the .gitlab-ci.yml as it is missing a dependency (nmigen-soc). 
I was able to run the test_microwatt.py and test_issuer without any errors.

@programmerjake the .gitlab-ci.yml says https://github.com/nmigen/nmigen.git, is this correct.
First I tried out https://github.com/nmigen/nmigen.git which says nmigen-0.1 then 
I tried out https://github.com/m-labs/migen which is nmigen-0.2.
I saw that you commited a bugfix to https://github.com/nmigen/nmigen so I assume that is the most recent version.

Tobias

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[libre-riscv-dev] daily kan-ban update 13jul2020

[Luke Kenneth Casson Leighton]

task list:

https://bugs.libre-soc.org/showdependencytree.cgi?maxdepth=1&id=383&hide_resolved=1

yesterday:

got a significant way running microwatt helloworld binary.  further
progress needs a 16550 UART.

today:

* closed a number of completed bugreports
* added unit tests for extswsli
* reported v3.0B spec bug
* started on formal proof for extswsli

l.



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