From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: Re: [libre-riscv-dev] using a stage chain in a stage
Date: Thu, 4 Jun 2020 02:32:09 +0100
Message-ID: <CAPweEDwNjCCQ7g1S3sr-WYPggc=3BKo2VAgVecJsqK=jWUMbhA@mail.gmail.com> (raw)
In-Reply-To: <CAPweEDwvg1bQ9MLxrk660J9v_DwssibnkYtyFJ_Mqvf-6NN_cg@mail.gmail.com>
https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/fu/div/pipe_data.py;hb=HEAD
sorry, CompLogicalOpSubset. unless carry-in, sticky overflow etc are
needed, which i don't think they are.
each subset grabs only the fields from the instruction decode
(Decode2Execute1Type) that the pipeline actually needs.
that subset is supposed to be dropped into ctx.op, see IntegerData class.
all ospec and ispec classes derive from IntegerData at the moment.
l.
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Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-04 0:52 Jacob Lifshay
2020-06-04 1:20 ` Luke Kenneth Casson Leighton
2020-06-04 1:30 ` Jacob Lifshay
2020-06-04 1:37 ` Luke Kenneth Casson Leighton
2020-06-04 1:32 ` Luke Kenneth Casson Leighton [this message]
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