From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: Re: [libre-riscv-dev] ppc-dev linux patch support for microwatt!
Date: Tue, 12 May 2020 02:25:43 +0100
Message-ID: <CAPweEDwWQ4L5zggNJyM0TvQxWbrcqU7W9J+AoBfj3dzdhObBRQ@mail.gmail.com> (raw)
In-Reply-To: <FEBBCA29-9C37-45EF-818F-E8705F2EEEC6@gatech.edu>
On Tuesday, May 12, 2020, Yehowshua <yimmanuel3@gatech.edu> wrote:
>
>
> > On May 11, 2020, at 8:53 PM, Luke Kenneth Casson Leighton <lkcl@lkcl.net>
> wrote:
> >
> > that is prohibited by design.
>
> Are you saying that the POWER ISA itself dis-allows writes to instruction
> memory?
we'll have to check the spec closely, or ask on one if the lists, or just
trust paul's expertise. he's been working with powerpc since 1996.
Does such a behavior get trapped or something?
hard exception, yes.
> I know that Linux on RISCV for example will set page r/w/ex bits that are
> part of the RISCV ISA. Then, an attempt to store into instruction memory
> becomes prohibited.
exactly.
l
--
---
crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
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Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-11 22:19 Luke Kenneth Casson Leighton
2020-05-11 22:23 ` Luke Kenneth Casson Leighton
2020-05-11 22:27 ` Yehowshua
2020-05-11 22:34 ` Luke Kenneth Casson Leighton
2020-05-11 22:53 ` Luke Kenneth Casson Leighton
2020-05-11 23:02 ` Yehowshua
2020-05-12 0:53 ` Luke Kenneth Casson Leighton
2020-05-12 0:56 ` Yehowshua
2020-05-12 1:25 ` Luke Kenneth Casson Leighton [this message]
2020-05-12 1:42 ` [libre-riscv-dev] Power memory fences and icache handling Jacob Lifshay
2020-05-12 3:29 ` Luke Kenneth Casson Leighton
2020-05-11 22:23 ` [libre-riscv-dev] ppc-dev linux patch support for microwatt! Yehowshua
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