From: Yehowshua <yimmanuel3@gatech.edu>
To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: Re: [libre-riscv-dev] ppc-dev linux patch support for microwatt!
Date: Mon, 11 May 2020 20:56:22 -0400
Message-ID: <FEBBCA29-9C37-45EF-818F-E8705F2EEEC6@gatech.edu> (raw)
In-Reply-To: <CAPweEDxHxc4ZWuQtEnY1EQqdRHuXAqgVXpLxqWRewXJdrPpcwA@mail.gmail.com>
> On May 11, 2020, at 8:53 PM, Luke Kenneth Casson Leighton <lkcl@lkcl.net> wrote:
>
> that is prohibited by design.
Are you saying that the POWER ISA itself dis-allows writes to instruction memory?
Does such a behavior get trapped or something?
I know that Linux on RISCV for example will set page r/w/ex bits that are part of the RISCV ISA. Then, an attempt to store into instruction memory becomes prohibited.
Yehowshua
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Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-11 22:19 Luke Kenneth Casson Leighton
2020-05-11 22:23 ` Luke Kenneth Casson Leighton
2020-05-11 22:27 ` Yehowshua
2020-05-11 22:34 ` Luke Kenneth Casson Leighton
2020-05-11 22:53 ` Luke Kenneth Casson Leighton
2020-05-11 23:02 ` Yehowshua
2020-05-12 0:53 ` Luke Kenneth Casson Leighton
2020-05-12 0:56 ` Yehowshua [this message]
2020-05-12 1:25 ` Luke Kenneth Casson Leighton
2020-05-12 1:42 ` [libre-riscv-dev] Power memory fences and icache handling Jacob Lifshay
2020-05-12 3:29 ` Luke Kenneth Casson Leighton
2020-05-11 22:23 ` [libre-riscv-dev] ppc-dev linux patch support for microwatt! Yehowshua
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