[libre-riscv-dev] ppc-dev linux patch support for microwatt!

[libre-riscv-dev] ppc-dev linux patch support for microwatt!

[Luke Kenneth Casson Leighton]

https://lists.ozlabs.org/pipermail/linuxppc-dev/2020-May/210525.html

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Re: [libre-riscv-dev] ppc-dev linux patch support for microwatt!

[Luke Kenneth Casson Leighton]

ahh :)
https://github.com/paulusmack/microwatt/blob/mmu/mmu.vhdl

On Mon, May 11, 2020 at 11:19 PM Luke Kenneth Casson Leighton
<lkcl@lkcl.net> wrote:
>
> https://lists.ozlabs.org/pipermail/linuxppc-dev/2020-May/210525.html
>
> ---
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Re: [libre-riscv-dev] ppc-dev linux patch support for microwatt!

[Yehowshua]

> On May 11, 2020, at 6:23 PM, Luke Kenneth Casson Leighton <lkcl@lkcl.net> wrote:
> 
> https://github.com/paulusmack/microwatt/blob/mmu/mmu.vhdl <https://github.com/paulusmack/microwatt/blob/mmu/mmu.vhdl>
Oh - its a fork. Haha
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Re: [libre-riscv-dev] ppc-dev linux patch support for microwatt!

[Luke Kenneth Casson Leighton]

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On Mon, May 11, 2020 at 11:27 PM Yehowshua <yimmanuel3@gatech.edu> wrote:
>
>
>
> > On May 11, 2020, at 6:23 PM, Luke Kenneth Casson Leighton <lkcl@lkcl.net> wrote:
> >
> > https://github.com/paulusmack/microwatt/blob/mmu/mmu.vhdl <https://github.com/paulusmack/microwatt/blob/mmu/mmu.vhdl>
> Oh - its a fork. Haha

yes, paul mackerras is working on the RADIX MMU implementation, and
has got a linux kernel booting.  that's really significant.  i can do
a brain-dead conversion of his mmu.vhdl and associated data structures
in a couple of hours: i'm not so good at writing unit tests etc. that
takes longer: if we work together we should have a linux-capable MMU
in a few days.

l.

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Re: [libre-riscv-dev] ppc-dev linux patch support for microwatt!

[Luke Kenneth Casson Leighton]

dcache:
https://github.com/paulusmack/microwatt/blob/mmu/dcache.vhdl

icache:
https://github.com/paulusmack/microwatt/blob/mmu/icache.vhdl

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Re: [libre-riscv-dev] ppc-dev linux patch support for microwatt!

[Yehowshua]

> dcache:
> https://github.com/paulusmack/microwatt/blob/mmu/dcache.vhdl <https://github.com/paulusmack/microwatt/blob/mmu/dcache.vhdl>
> 
> icache:
> https://github.com/paulusmack/microwatt/blob/mmu/icache.vhdl <https://github.com/paulusmack/microwatt/blob/mmu/icache.vhdl>


I was actually talking to Michael about that the other day.

If you have an instruction that does a store to a location in the icache, I guess you need some coherency to make that work.

Yehowshua
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Re: [libre-riscv-dev] ppc-dev linux patch support for microwatt!

[Luke Kenneth Casson Leighton]

On Tuesday, May 12, 2020, Yehowshua <yimmanuel3@gatech.edu> wrote:

> > dcache:
> > https://github.com/paulusmack/microwatt/blob/mmu/dcache.vhdl <
> https://github.com/paulusmack/microwatt/blob/mmu/dcache.vhdl>
> >
> > icache:
> > https://github.com/paulusmack/microwatt/blob/mmu/icache.vhdl <
> https://github.com/paulusmack/microwatt/blob/mmu/icache.vhdl>
>
>
> I was actually talking to Michael about that the other day.
>
> If you have an instruction that does a store to a location in the icache,


that is prohibited by design.

 I guess you need some coherency to make that work.


single core and separate read only instruction area from readwrite data
area, no you don't.

 l.



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Re: [libre-riscv-dev] ppc-dev linux patch support for microwatt!

[Yehowshua]

> On May 11, 2020, at 8:53 PM, Luke Kenneth Casson Leighton <lkcl@lkcl.net> wrote:
> 
> that is prohibited by design.

Are you saying that the POWER ISA itself dis-allows writes to instruction memory?
Does such a behavior get trapped or something?

I know that Linux on RISCV for example will set page r/w/ex bits that are part of the RISCV ISA. Then, an attempt to store into instruction memory becomes prohibited.

Yehowshua
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Re: [libre-riscv-dev] ppc-dev linux patch support for microwatt!

[Luke Kenneth Casson Leighton]

On Tuesday, May 12, 2020, Yehowshua <yimmanuel3@gatech.edu> wrote:

>
>
> > On May 11, 2020, at 8:53 PM, Luke Kenneth Casson Leighton <lkcl@lkcl.net>
> wrote:
> >
> > that is prohibited by design.
>
> Are you saying that the POWER ISA itself dis-allows writes to instruction
> memory?


we'll have to check the spec closely, or ask on one if the lists, or just
trust paul's expertise.  he's been working with powerpc since 1996.

Does such a behavior get trapped or something?


hard exception, yes.


> I know that Linux on RISCV for example will set page r/w/ex bits that are
> part of the RISCV ISA. Then, an attempt to store into instruction memory
> becomes prohibited.


exactly.

l



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[libre-riscv-dev] Power memory fences and icache handling

[Jacob Lifshay]

On Mon, May 11, 2020, 17:54 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
wrote:

> On Tuesday, May 12, 2020, Yehowshua <yimmanuel3@gatech.edu> wrote:
>
> > > dcache:
> > > https://github.com/paulusmack/microwatt/blob/mmu/dcache.vhdl <
> > https://github.com/paulusmack/microwatt/blob/mmu/dcache.vhdl>
> > >
> > > icache:
> > > https://github.com/paulusmack/microwatt/blob/mmu/icache.vhdl <
> > https://github.com/paulusmack/microwatt/blob/mmu/icache.vhdl>
> >
> >
> > I was actually talking to Michael about that the other day.
> >
> > If you have an instruction that does a store to a location in the icache,
>
>
> that is prohibited by design.
>

If you're trying to run a standard Linux OS, writing to memory that could
be in the icache is required, that's how the dynamic linker works.
Additionally, loading code from disk (e.g. the exec() call) or JIT
compilation also requires writing to memory then executing it. In all of
those cases one or more icache invalidate and then an isync instruction (or
other context synchronizing instruction) are run before running the
modified code.

Note: it turns out that isync doesn't do any icache flushing without
additional icache invalidate instructions, so it's not quite as expensive
as I had originally thought for Power atomics, however, it still restarts
fetching and decoding instructions, so is still more expensive than
necessary for just using it as an atomic fence.

It's standard practice for JITs to map a section of memory with all of R/W
and execute permissions simultaneously, then, once a section of code is
written/modified, it will run the required icache invalidate and isync
instructions (RISC-V just uses a single fence.i instruction that must be
run on all harts using a syscall) before trying to execute the changed code.

Jacob

>
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Re: [libre-riscv-dev] Power memory fences and icache handling

[Luke Kenneth Casson Leighton]

On Tuesday, May 12, 2020, Jacob Lifshay <programmerjake@gmail.com> wrote:

> On Mon, May 11, 2020, 17:54 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
> wrote:
>
> > On Tuesday, May 12, 2020, Yehowshua <yimmanuel3@gatech.edu> wrote:
> >
> > > > dcache:
> > > > https://github.com/paulusmack/microwatt/blob/mmu/dcache.vhdl <
> > > https://github.com/paulusmack/microwatt/blob/mmu/dcache.vhdl>
> > > >
> > > > icache:
> > > > https://github.com/paulusmack/microwatt/blob/mmu/icache.vhdl <
> > > https://github.com/paulusmack/microwatt/blob/mmu/icache.vhdl>
> > >
> > >
> > > I was actually talking to Michael about that the other day.
> > >
> > > If you have an instruction that does a store to a location in the
> icache,
> >
> >
> > that is prohibited by design.
> >
>
> If you're trying to run a standard Linux OS, writing to memory that could
> be in the icache is required, that's how the dynamic linker works.


my understabding of this is that writing to memory as a data page, then
flushing it and reloading it into the icache, is a workaround.


> Additionally, loading code from disk (e.g. the exec() call) or JIT
> compilation also requires writing to memory then executing it. In all of
> those cases one or more icache invalidate and then an isync instruction (or
> other context synchronizing instruction) are run before running the
> modified code.


that would... ok if the icache is entirely invalidated following a write
through the dcache, it would load  the modified executable


>
> Note: it turns out that isync doesn't do any icache flushing without
> additional icache invalidate instructions, so it's not quite as expensive
> as I had originally thought for Power atomics, however, it still restarts
> fetching and decoding instructions, so is still more expensive than
> necessary for just using it as an atomic fence.


hmmm




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Re: [libre-riscv-dev] ppc-dev linux patch support for microwatt!

[Yehowshua]

> On May 11, 2020, at 6:19 PM, Luke Kenneth Casson Leighton <lkcl@lkcl.net> wrote:
> 
> https://lists.ozlabs.org/pipermail/linuxppc-dev/2020-May/210525.html

Either they're emulating an MMU or processes can corrupt one another…

Either way, looks like we have a Masochistic safe-plug solution for demo day if we we haven’t yet finished the hypervisor or MMU, and we wish to show more than micro python.

Yehowshua
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