From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: [libre-riscv-dev] LD/ST CompUnit "working"
Date: Sat, 9 May 2020 00:18:32 +0100
Message-ID: <CAPweEDwYvUrkhgNw1GUAVS6tS0P8hGz=5Hn5KNgobnCC14brnQ@mail.gmail.com> (raw)
i've got a basic unit test operational with the LD/ST Comp Unit,
performing 3 STs then 3 LDs using indexed and immediates. it goes via
PortInterface.
one issue we have here is that until there is a parallel-capable
L0CacheBuffer, interactions between multiple LDs or multiple STs
cannot be tested, because the "test" L0CacheBuffer can only handle one
and only one memory request. this is... sort-of "fine" (functional,
but performance will suck).
i will do "update" mode (output the computed Effective Address) tomorrow.
l.
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Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-08 23:18 Luke Kenneth Casson Leighton [this message]
2020-05-08 23:21 ` Jacob Lifshay
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