[libre-riscv-dev] LD/ST CompUnit "working"

[libre-riscv-dev] LD/ST CompUnit "working"

[Luke Kenneth Casson Leighton]

i've got a basic unit test operational with the LD/ST Comp Unit,
performing 3 STs then 3 LDs using indexed and immediates.  it goes via
PortInterface.

one issue we have here is that until there is a parallel-capable
L0CacheBuffer, interactions between multiple LDs or multiple STs
cannot be tested, because the "test" L0CacheBuffer can only handle one
and only one memory request.  this is... sort-of "fine" (functional,
but performance will suck).

i will do "update" mode (output the computed Effective Address) tomorrow.

l.

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Re: [libre-riscv-dev] LD/ST CompUnit "working"

[Jacob Lifshay]

On Fri, May 8, 2020, 16:19 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
wrote:

> i've got a basic unit test operational with the LD/ST Comp Unit,
> performing 3 STs then 3 LDs using indexed and immediates.  it goes via
> PortInterface.
>

Yay! sorry I'm taking soo long...

Jacob
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