From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: Re: [libre-riscv-dev] MultiCompUnit- ALU interaction. was: daily kan-ban update 30may2020
Date: Sat, 30 May 2020 20:05:32 +0100
Message-ID: <CAPweEDwmhzsYBjHPQ9hbB5pJaFKXTNXGw6ZaWaz8bF1D9Ga24Q@mail.gmail.com> (raw)
In-Reply-To: <CAPweEDxUtX=uFFTbYu7nSHOAMUSeLQ6yaDF1ZNrO5COkOL+cBQ@mail.gmail.com>
On Sat, May 30, 2020 at 7:06 PM Luke Kenneth Casson Leighton
<lkcl@lkcl.net> wrote:
> it will currently fail at the extsb unit test because the MCU expects *all* operands (non-optionally) to be requested from the regfile, and extsb does not have RB.
sorted. a "source operand read mask" is now passed in to the
MultiCompUnit, telling it *not* to request specific register file
ports that are not actually required.
should now complete without error:
$ python3 fu/compunits/test/test_alu_compunit.py
next phase: the write-side. again: just as read-ports should not be
requested which are not required, neither should write-ports.
l.
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Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-30 17:40 Luke Kenneth Casson Leighton
2020-05-30 17:50 ` Yehowshua
2020-05-30 18:06 ` Luke Kenneth Casson Leighton
2020-05-30 19:05 ` Luke Kenneth Casson Leighton [this message]
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