Re: [libre-riscv-dev] MultiCompUnit- ALU interaction. was: daily kan-ban update 30may2020

[Luke Kenneth Casson Leighton <lkcl@lkcl.net>]

On Saturday, May 30, 2020, Yehowshua <yimmanuel3@gatech.edu> wrote:

> When you say you got something working, do you mean that you got the
> decoder to decode, the issuer to issue, and the ALU FU to compute? All
> working together?


the interaction - the interface - between MultiCompUnit (a data "monitor"
aka Reservation Station) and a pipelined ALU.

MCU is a massively complex and compact FSM (the LDST CompUnit equally so).

it must:

* handle multiple ready/valid signalling to bring in multiple (optional)
operands from the regfile
* then use ready/valid signalling to kick off the ALU
* *WAIT* for ready/valid signalling from the ALU and capture the output
* finally use *yet more* ready/valid signalling to independently
acknowledge every single output being sent to its corresponding regfile for
write.

all of that *back-propagates* such that if the ALU *OUTPUT* is not ready,
the incoming data to the ALU must not be sent.

and every single one of those ready/valid events can occur independently at
any time.

and some of them are optional at the input phase.

and some of them are optional at the output phase.

it is quite ridiculously complex for such a relatively small amount of code.



> If this is the case, how can I make the codebase do this myself?


$ cd soc/src/soc
$ python3 fu/compunits/test/test_alu_compunit.py

it will currently fail at the extsb unit test because the MCU expects *all*
operands (non-optionally) to be requested from the regfile, and extsb does
not have RB.

l.




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