* [libre-riscv-dev] auto-generated simulator working??
@ 2020-04-05 20:19 Luke Kenneth Casson Leighton
2020-04-05 21:44 ` Jacob Lifshay
0 siblings, 1 reply; 3+ messages in thread
From: Luke Kenneth Casson Leighton @ 2020-04-05 20:19 UTC (permalink / raw)
To: Libre-RISCV General Development
moo? it's working? holy cow!
def test_load_store(self):
lst = ["addi 1, 0, 0x0010",
"addi 2, 0, 0x1234",
"stw 2, 0(1)",
"lwz 3, 0(1)"]
(SelectableInt(value=0x1234, bits=64),)
writing reg 3
reg 0 00000000 00000010 00001234 00001234 00000000 00000000 00000000 00000000
reg 8 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
reg 16 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
reg 24 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
SelectableInt(value=0x10, bits=64)
.
----------------------------------------------------------------------
Ran 3 tests in 1.918s
OK
_______________________________________________
libre-riscv-dev mailing list
libre-riscv-dev@lists.libre-riscv.org
http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [libre-riscv-dev] auto-generated simulator working??
2020-04-05 20:19 [libre-riscv-dev] auto-generated simulator working?? Luke Kenneth Casson Leighton
@ 2020-04-05 21:44 ` Jacob Lifshay
2020-04-05 22:22 ` Luke Kenneth Casson Leighton
0 siblings, 1 reply; 3+ messages in thread
From: Jacob Lifshay @ 2020-04-05 21:44 UTC (permalink / raw)
To: Libre-RISCV General Development
On Sun, Apr 5, 2020 at 1:20 PM Luke Kenneth Casson Leighton
<lkcl@lkcl.net> wrote:
>
> moo? it's working? holy cow!
Yay!!
_______________________________________________
libre-riscv-dev mailing list
libre-riscv-dev@lists.libre-riscv.org
http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [libre-riscv-dev] auto-generated simulator working??
2020-04-05 21:44 ` Jacob Lifshay
@ 2020-04-05 22:22 ` Luke Kenneth Casson Leighton
0 siblings, 0 replies; 3+ messages in thread
From: Luke Kenneth Casson Leighton @ 2020-04-05 22:22 UTC (permalink / raw)
To: Libre-RISCV General Development
On Sunday, April 5, 2020, Jacob Lifshay <programmerjake@gmail.com> wrote:
> On Sun, Apr 5, 2020 at 1:20 PM Luke Kenneth Casson Leighton
> <lkcl@lkcl.net> wrote:
> >
> > moo? it's working? holy cow!
>
> Yay!!
good job by michael, integrating the autogenerator real fast.
this basically cuts months off of creating a simulator.
we have now like... 200 opcodes? only 4 of them tested, mind :) but that's
200 opcodes in *under 10 days*
if we implement the PC and the CR flags it will be possible to execute mini
programs.
l.
--
---
crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
_______________________________________________
libre-riscv-dev mailing list
libre-riscv-dev@lists.libre-riscv.org
http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, back to index
Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-04-05 20:19 [libre-riscv-dev] auto-generated simulator working?? Luke Kenneth Casson Leighton
2020-04-05 21:44 ` Jacob Lifshay
2020-04-05 22:22 ` Luke Kenneth Casson Leighton
Libre RISC-V Mailing list Archives (accessible via public-inbox)
Archives are clonable: git clone --mirror https://inbox.libre-soc.org/libre-riscv-dev
Example config snippet for mirrors
AGPL code for this site: git clone https://public-inbox.org/public-inbox.git