Re: [libre-riscv-dev] RISCV-V Extension

From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: Re: [libre-riscv-dev] RISCV-V Extension
Date: Wed, 20 May 2020 18:05:59 +0100
Message-ID: <CAPweEDxFEcdrPfCt93XCmRxHv6sDvehsHmJ1-fvFKMJVz+92+g@mail.gmail.com> (raw)
In-Reply-To: <C8102C6D-A60C-4D99-811D-941AAC7561D0@gatech.edu>

On Wed, May 20, 2020 at 5:31 PM Yehowshua <yimmanuel3@gatech.edu> wrote:
>
> It seems pretty similar to SimpleV.

yes.  i tracked what they were doing, and based VL, SUBVL, predication
etc. and many other aspects: data-dependent fail-on-first and so on.

> Register Length agnostic vector instructions that then get unrolled onto hardware as necessary.

actually the assumption is that there are hardware "lanes" and that if
there is a mismatch between VL (=2, =3) and the "Lanes" (4) those
non-matching "Lanes" run empty.

this is a fundamental design assumption, that although setting VL
*requests* a number of elements to be processed, the hardware does not
have to do exactly what is requested: it may assign any non-zero
*actual* VL.

luckily all loop assembly code is specifically designed to be
independent of what the hardware actually sets VL to on any given
loop.

l.

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