From: Yehowshua <yimmanuel3@gatech.edu>
To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: [libre-riscv-dev] RISCV-V Extension
Date: Wed, 20 May 2020 12:31:30 -0400
Message-ID: <C8102C6D-A60C-4D99-811D-941AAC7561D0@gatech.edu> (raw)
It seems pretty similar to SimpleV.
Register Length agnostic vector instructions that then get unrolled onto hardware as necessary.
https://gms.tf/riscv-vector.html <https://gms.tf/riscv-vector.html>
Yehowshua
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Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-20 16:31 Yehowshua [this message]
2020-05-20 17:05 ` Luke Kenneth Casson Leighton
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