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From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: [libre-riscv-dev] LDST compunit semi operational
Date: Wed, 10 Jun 2020 18:27:56 +0100
Message-ID: <CAPweEDxGSN7HC4muGHA7eznvZdNseg-JyX5hNA6a=Au_thzxCA@mail.gmail.com> (raw)

i've managed to get the addresses split into LSBs and MSBs, and use the
lower 3 bits in conjunction with the Data Length for a bitmap mask on
writing, and as a corresponding bytemap mask for read.

this via the dummy / nonproduction L0CacheBuffer, which does not cope with
misalignment crossing a 64 bit boundary.

fortunately, nmigen Memory can be passed an *array* of write-enable lines,
and so can wishbone.

i could really use some help on this code as it is particularly complex and
also critical to get right.

l.



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