[libre-riscv-dev] CORDIC importance

[libre-riscv-dev] CORDIC importance

[Michael Nolan]

Luke,

I know we're tight on time for the tapeout in October. Is there 
something that would be better for me to work on right now than the cordic?

Thanks,

Michael


_______________________________________________
libre-riscv-dev mailing list
libre-riscv-dev@lists.libre-riscv.org
http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev

Re: [libre-riscv-dev] CORDIC importance

[Luke Kenneth Casson Leighton]

On Tue, May 5, 2020 at 6:33 PM Michael Nolan <mtnolan2640@gmail.com> wrote:
>
> Luke,
>
> I know we're tight on time for the tapeout in October. Is there
> something that would be better for me to work on right now than the cordic?

actually probably yes - although we do really need SIN, COS (etc.)

* cyclic buffer for the regfile.  https://bugs.libre-soc.org/show_bug.cgi?id=296
* simulator (still needed, to "track" the hardware so i know what to
design!) in particular, the branch unit.  which first needs carry-in
and carry-out (CR0 etc.)
* an actual pipelined ALU, that expands on the alu_hier.py concept and
adds more functions - however it also needs to use PartitionedSignal.
this can default to "all off" initially.
* a 128-to-64 Wishbone Arbiter.  take in 128 bit read/write requests,
split them into 2 separate 64-bit Wishbone read/write requests, but
use a bit per half (HI-64, LO-64) to indicate "we do or do not" need
this half to go out.

later (not much later) we will need:

* a RADIX MMU lookup system (POWER-compliant)
* a TLB that caches RADIX lookups

you're almost certainly going to find a nmigen or migen Wishbone
Arbiter out there somewhere already, there may even be one in minerva
already.

l.

_______________________________________________
libre-riscv-dev mailing list
libre-riscv-dev@lists.libre-riscv.org
http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev