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From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: [libre-riscv-dev] daily kan-ban update 01aug2020
Date: Sat, 1 Aug 2020 18:58:55 +0100
Message-ID: <CAPweEDxNBah24TSdRe20dhSsRbB5sO56FbjJ32FpV78HMJ3vUA@mail.gmail.com> (raw)

tasks:

*
https://bugs.libre-soc.org/showdependencytree.cgi?maxdepth=1&id=383&hide_resolved=1

yesterday:

* exploring litex libresoc simulation, found several bugs

today:

* looked at shiftrot formal proof
* continued litex simulation investigation

finding out what is going on in litex is hampered significantly by not
being able to do side-by-side comparisons.

therefore what i am going to do is add a dmi interface to libresoc and get
the litex sim to single-step then dump registers.  with a compatible dmi
interface the same sim code FSM will be useable on both types of core.

discrepancies should then be easy to spot by using diff on the two debug
logs.

at that point i will know which instruction is wrong, where right now it is
excruciating guesswork.

l.




-- 
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