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From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: Re: [libre-riscv-dev] daily kan-ban update 31may2020
Date: Sun, 31 May 2020 16:13:32 +0100
Message-ID: <CAPweEDyMAFL3f48g1gL8tUsx8K7FsOASjr83a3xqo0WAMLhmaw@mail.gmail.com> (raw)
In-Reply-To: <CAPweEDznJw-y=VJE=q0RbDcJ5LPGJ6wpv7ADq4Ek2hfAnXPUTA@mail.gmail.com>

On Sun, May 31, 2020 at 2:38 PM Luke Kenneth Casson Leighton
<lkcl@lkcl.net> wrote:

> today:
>
> * finding numerous errors where register-writes are being requested by
> the ALU pipeline, where the data is *not* valid ("ok" signal set when
> it should not be)

HA!  tracked down and fixed a bug in MultiCompUnit's (new) write-mask
handling, where there was a test condition looking for write-request
signals coming in that would, because they were disabled, never going
to happen.

once that was sorted, the new CompUnit-based unit test for ALU passed.
it uses the exact same unit tests as from the pipeline-only-based ALU
unit test.

with the only difference between the tests being that one adds
MultiCompUnit on *top* of the other, this helps to confirm that
MultiCompUnit is functional.

i am very happy.

i'll do the same thing for the other pipelines.

l.

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Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-05-31 13:38 Luke Kenneth Casson Leighton
2020-05-31 15:13 ` Luke Kenneth Casson Leighton [this message]
2020-05-31 20:12 ` Tobias Platen
2020-05-31 22:14   ` Luke Kenneth Casson Leighton

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