From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: [libre-riscv-dev] daily kan-ban update 27may2020
Date: Wed, 27 May 2020 13:25:06 +0100
Message-ID: <CAPweEDz+i8kW_HKmC+8_-ivENigOtpuXTnvODD_kUUn784TTcA@mail.gmail.com> (raw)
yesterday:
* altered VirtualRegPort to simplify it and got a proof of concept unit
test, enough to be happy to move on
* added CR and XER regfiles (using VirtualRegPort) and also a Fast Regfile
(PC, LR, CTR, MSR). the Fast regfile is going to be a handful. 3R3W (maybe
more), no way we can use SRAMs.
morning:
* reviewed Tobias's DataMerger class. principle looks good.
* answered Cole about regfile proofs. we work on them together.
* reviewed Systemes Libre Company.
today:
* collaborate with Cole with regfile proofs
* help Cesar with parallel compunit test
* read proof_fu.py again
* do a unit test similar to test_pipe_caller.py which uses MultiCompUnit
derivatives.
--
---
crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
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Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-27 12:25 Luke Kenneth Casson Leighton [this message]
2020-05-27 16:35 ` Cole Poirier
2020-05-27 17:29 ` Tobias Platen
2020-05-27 18:42 ` Luke Kenneth Casson Leighton
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