[libre-riscv-dev] daily kan-ban update 27may2020

[libre-riscv-dev] daily kan-ban update 27may2020

[Luke Kenneth Casson Leighton]

yesterday:

* altered VirtualRegPort to simplify it and got a proof of concept unit
test, enough to be happy to move on
* added CR and XER regfiles (using VirtualRegPort) and also a Fast Regfile
(PC, LR, CTR, MSR). the Fast regfile is going to be a handful.  3R3W (maybe
more), no way we can use SRAMs.

morning:

* reviewed Tobias's DataMerger class.  principle looks good.
* answered Cole about regfile proofs.  we work on them together.
* reviewed Systemes Libre Company.

today:

* collaborate with Cole with regfile proofs
* help Cesar with parallel compunit test
* read proof_fu.py again
* do a unit test similar to test_pipe_caller.py which uses MultiCompUnit
derivatives.



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Re: [libre-riscv-dev] daily kan-ban update 27may2020

[Cole Poirier]

Yesterday:

Studied virtual_port.py to understand nmigen, hdl, and hardware better
because its the full implementation of something I tried to implement
but really struggled to understand. Being able to compare my effort on
this to the end product is nearly as helpful to my learning as was the
tremendous amount of help Michael and Luke provided working through
writing bpermd.py and proof_bpermd.py. Thank you.

I also started working through the very basic first assertions for the
formal proof of Register, RegFile, and RegFileArray from
regfile/regfile.py, which I will work on with Luke today.

Cole


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Re: [libre-riscv-dev] daily kan-ban update 27may2020

[Tobias Platen]

morning:
elaborate function for DataMerger

today:
reading l0_cache.py

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Re: [libre-riscv-dev] daily kan-ban update 27may2020

[Luke Kenneth Casson Leighton]

On Wednesday, May 27, 2020, Tobias Platen <libre-soc@platen-software.de>
wrote:

> morning:
> elaborate function for DataMerger


you may have missed that i left some review comments in 216?

l.



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