[libre-riscv-dev] daily kan-ban update 11jul2020

[libre-riscv-dev] daily kan-ban update 11jul2020

[Luke Kenneth Casson Leighton]

task list:

https://bugs.libre-soc.org/showdependencytree.cgi?maxdepth=1&id=383&hide_resolved=1

yesterday:

* sorting out div, particularly overflow.
* helping samuel get up and running

today:

* tracked down issue with whitequark that jacob highlighted, on vcd files
* added "overflow calculation" to MUL pseudocode
* added more MUL unit tests


i'm starting to become reasonably confident that MUL and DIV are
functionally correct.  checking against first qemu then actual POWER9 would
help with that.

the only downside being that the blocks are so massive that we can't
realistically use them as-is.  however the unit tests give us a baseline to
"codemorph" against.

still the biggest next milestone is being able to select littlend/bigend
code in order to run microwatt unit tests.  still thinking that through.

l.



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Re: [libre-riscv-dev] daily kan-ban update 11jul2020

[Luke Kenneth Casson Leighton]

On Saturday, July 11, 2020, Luke Kenneth Casson Leighton <lkcl@lkcl.net>
wrote:

>
> still the biggest next milestone is being able to select littlend/bigend
> code in order to run microwatt unit tests.  still thinking that through.
>

for now i have set up a module with a single global flag that everything
uses.  this can be changed later to respect the appropriate MSR bit.

i identified that in PowerDecoder the instruction byte swapping was
inverted.  correcting this brought the decoder into line with qemu and with
microwatt test binaries.

the next phase was to track down a bug in core.py where rather than take
the conditional output from the CompUnit i had connected directly to the
pipeline ALU output.

the pipeline output obvuously changes depending on what cycle is currently
being executed, resulting in data corruption.

whereas the CompUnit Manager's entire job is to latch that data at the
correct point in time, then present it to the Regfile Bus on request.

this allowed me to progress to another bug that i will investigate
tomorrow.  there may be a ST instruction missing from the CSV files, i have
to track it down.

l.



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