From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: Re: [libre-riscv-dev] Following the PowerISA
Date: Mon, 6 Apr 2020 11:51:07 +0100
Message-ID: <CAPweEDzMoDtmpB-oE0oOJkxmEwAzgaKnAPtZbEzQtc+vy4UsBQ@mail.gmail.com> (raw)
In-Reply-To: <68333793-489F-4F74-88C2-7DA0BCA206A6@gatech.edu>
On Mon, Apr 6, 2020 at 3:46 AM Immanuel, Yehowshua U
<yimmanuel3@gatech.edu> wrote:
>
> On the website, we have:
>
> > The Libre RISC-V Project is building a hybrid CPU/GPU SoC. As the name of the project implies,
> > we will be following the RISC-V ISA due to it being open-source and also because of the huge
> > software and hardware ecosystem building around it.
>
> Since we are now doing userspace RISCV+POWER and system-wide POWER, I imagine this section should be updated?
https://git.libre-riscv.org/?p=crowdsupply.git;a=commitdiff;h=69576cbd0ca58e98ebbf525d827b377fe7ad04fc
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Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-06 2:46 Immanuel, Yehowshua U
2020-04-06 2:51 ` Immanuel, Yehowshua U
2020-04-06 3:40 ` Immanuel, Yehowshua U
2020-04-06 6:28 ` Immanuel, Yehowshua U
2020-04-06 7:02 ` Jacob Lifshay
2020-04-06 10:58 ` Luke Kenneth Casson Leighton
2020-04-06 10:51 ` Luke Kenneth Casson Leighton [this message]
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