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From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: Re: [libre-riscv-dev] Handling POWERVec Instructions
Date: Thu, 11 Jun 2020 22:52:06 +0100
Message-ID: <CAPweEDzTtk6Wv102KxSA+WsQ7EcGUwghcf-kZCJd8o9QPuYhag@mail.gmail.com> (raw)
In-Reply-To: <88CA99A5-7D8B-49CA-831F-771326724507@gatech.edu>

On Thu, Jun 11, 2020 at 10:21 PM Yehowshua <yimmanuel3@gatech.edu> wrote:
>
> Just spitballing here…
>
> But what we could do is trap and then scan the next 1024 instruction in software and JIT to SimpleV.

it sounds reasonable enough to me.  could be done as a parallel
project in a simulator.

l.

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Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-06-11 21:21 Yehowshua
2020-06-11 21:52 ` Luke Kenneth Casson Leighton [this message]

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