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From: Yehowshua <yimmanuel3@gatech.edu>
To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: [libre-riscv-dev] Handling POWERVec Instructions
Date: Thu, 11 Jun 2020 17:21:49 -0400
Message-ID: <88CA99A5-7D8B-49CA-831F-771326724507@gatech.edu> (raw)

Just spitballing here…

But what we could do is trap and then scan the next 1024 instruction in software and JIT to SimpleV.

Maybe we should modify the Linux ELF loader so that in general, it scans binaries for any POWER instructions before placing them into memory, and if it sees any, it passes the binary to a POWERVec -> SimpleV jitter.

Jilting isn’t all that bad - after all - Android does it - and we only need it IF we have POWER instructions - which for most SBC use cases - is probably pretty rare.

Yehowshua
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Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-06-11 21:21 Yehowshua [this message]
2020-06-11 21:52 ` Luke Kenneth Casson Leighton

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