[libre-riscv-dev] Handling POWERVec Instructions

[libre-riscv-dev] Handling POWERVec Instructions

[Yehowshua]

Just spitballing here…

But what we could do is trap and then scan the next 1024 instruction in software and JIT to SimpleV.

Maybe we should modify the Linux ELF loader so that in general, it scans binaries for any POWER instructions before placing them into memory, and if it sees any, it passes the binary to a POWERVec -> SimpleV jitter.

Jilting isn’t all that bad - after all - Android does it - and we only need it IF we have POWER instructions - which for most SBC use cases - is probably pretty rare.

Yehowshua
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Re: [libre-riscv-dev] Handling POWERVec Instructions

[Luke Kenneth Casson Leighton]

On Thu, Jun 11, 2020 at 10:21 PM Yehowshua <yimmanuel3@gatech.edu> wrote:
>
> Just spitballing here…
>
> But what we could do is trap and then scan the next 1024 instruction in software and JIT to SimpleV.

it sounds reasonable enough to me.  could be done as a parallel
project in a simulator.

l.

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