From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
To: Chris Harding <sjrct@protonmail.com>,
Libre-RISCV General Development
<libre-riscv-dev@lists.libre-riscv.org>
Subject: Re: [libre-riscv-dev] Hello!
Date: Thu, 12 Mar 2020 23:23:20 +0000
Message-ID: <CAPweEDzy69Nw95+cYOus1jy0nU1vU+9nd=HtrNzodYTg6hpD=A@mail.gmail.com> (raw)
In-Reply-To: <CAPweEDy5y_crPcvD6FL0UMvR+h8D_htubO-qZ7jdc+Y8rbVWJg@mail.gmail.com>
On Tuesday, March 10, 2020, Luke Kenneth Casson Leighton <lkcl@lkcl.net>
wrote:
>
> you'll like these
> https://git.libre-riscv.org/?p=riscv-tests.git;a=blob;f=
> isa/rv64ui/sv_addi_predicated_subvl.S;h=ea30797a70675e3fabd73ee66b7ee6
> 8d470aca58;hb=refs/heads/sv
so, that, chris, is an entirely new and innovative design of vectorisation,
which is best described as a "hardware for-loop".
the PC *pauses* whilst a loop counter generates *multiple* instructions,
using the one at the current PC as a template, increasing the register
numbers by one each time round the loop.
no more extending and duplicating ISAs with vector and vector-scalar
opcodes.
no more SIMD madness.
just *scalar* instructions... in a loop.
l.
--
---
crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
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