* Re: [libre-riscv-dev] Hello!
[not found] ` <CAPweEDy5y_crPcvD6FL0UMvR+h8D_htubO-qZ7jdc+Y8rbVWJg@mail.gmail.com>
@ 2020-03-12 23:23 ` Luke Kenneth Casson Leighton
0 siblings, 0 replies; only message in thread
From: Luke Kenneth Casson Leighton @ 2020-03-12 23:23 UTC (permalink / raw)
To: Chris Harding, Libre-RISCV General Development
On Tuesday, March 10, 2020, Luke Kenneth Casson Leighton <lkcl@lkcl.net>
wrote:
>
> you'll like these
> https://git.libre-riscv.org/?p=riscv-tests.git;a=blob;f=
> isa/rv64ui/sv_addi_predicated_subvl.S;h=ea30797a70675e3fabd73ee66b7ee6
> 8d470aca58;hb=refs/heads/sv
so, that, chris, is an entirely new and innovative design of vectorisation,
which is best described as a "hardware for-loop".
the PC *pauses* whilst a loop counter generates *multiple* instructions,
using the one at the current PC as a template, increasing the register
numbers by one each time round the loop.
no more extending and duplicating ISAs with vector and vector-scalar
opcodes.
no more SIMD madness.
just *scalar* instructions... in a loop.
l.
--
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