[libre-riscv-dev] Named Records in nMigen

[libre-riscv-dev] Named Records in nMigen

[Yehowshua]

Does anybody know if its possible to have a named records or subsignals in nMigen?
Consider mysig


I’d like to do something to the effect of 

```
>>> mysig.byte1
mysig[0:4]
```

Yehowshua
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Re: [libre-riscv-dev] Named Records in nMigen

[Yehowshua]

Actually - scratch that - I got it working fine.

Yehowshua

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Re: [libre-riscv-dev] Named Records in nMigen

[Jock Tanner]

Yehowshua,

In case you or anybody else come back to this question eventually: it
is possible to define a subsignal using built-in `slice()`. For
example, if the bits 4-7 of your instruction defines a source register,
you can do something similar to

  INSTR_SRC = slice(4, 8)

  # ...

  m.d.comb += self.src_reg.eq(instr[INSTR_SRC])

... or even wrap slices in standard `enum.Enum`:

  class InstrFormat(Enum):
    dst = slice(4)
    src = slice(4, 8)
    # ...

  m.d.comb += self.src_reg.eq(instr[InstrFormat.src])

Hope it helps.

On Mon, 2020-06-01 at 02:33 -0400, Yehowshua wrote:
> Actually - scratch that - I got it working fine.
> 
> Yehowshua
> 
> _______________________________________________
> libre-riscv-dev mailing list
> libre-riscv-dev@lists.libre-riscv.org
> http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev


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Re: [libre-riscv-dev] Named Records in nMigen

[Luke Kenneth Casson Leighton]

On Mon, Jun 1, 2020 at 7:29 AM Yehowshua <yimmanuel3@gatech.edu> wrote:
>
> Does anybody know if its possible to have a named records

Record.  give each bit (or bit range) a name and it is possible to
either assign (eq) to each bit (or bit range) *or* to the entire
thing.  bear in mind caveat (1) below.


> or subsignals in nMigen?

as Jock says: python slice, and use an Enum or a defined (named) constant.

bear in mind the following:

* Record is treated as a sequence of bits... *not* a sequence of
fields. several people objected to this, and whitequark to her credit
finally listened. however the replacement for Record is still under
development.

* RecordObject was created to allow for an over-ride of the behaviour
of Record, providing us with the ability to actually have something
more like python OO behaviour.

* you can use Cat on *BOTH* sides of the equation.  *PAY ATTENTION* to
the LSB-MSB ordering.  Cat is in *LSB* sequential ordering starting
from the 1st argument, where numbers, in the ENGLISH LANGUAGE, start
from the *MSB*.

   m.d.comb += Cat(mysig[0], mysig[5], mysig[6]).eq(Const(0b110, 3)

is equivalent to:

   m.d.comb += mysig[0].eq(0)
   m.d.comb += mysig[5].eq(1)
   m.d.comb += mysig[6].eq(1)

* to cope with both POWER9 LE/BE and also to help with ISA field
decoding, we created something that allows for "remapping" of fields.
it's called SignalBitRange.  this allows you to *remap* a sequence of
bits to completely different ranges.

l.

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