[libre-riscv-dev] [Bug 138] NLNet 2019 Coriolis2 Layout proposal 2019-10-029

[libre-riscv-dev] [Bug 138] NLNet 2019 Coriolis2 Layout proposal 2019-10-029

[bugzilla-daemon]

https://bugs.libre-soc.org/show_bug.cgi?id=138

--- Comment #11 from Luke Kenneth Casson Leighton <lkcl@lkcl.net> ---
Sentence for MoU:

Reducing complexity makes software and hardware we rely on to provide crucial
services and infrastructure more secure and reliable. Making sure that not only
the tools to develop ASICs (coriolis2) but the ASIC itself is fully
transparently developed leaves no opportunity for subversion of hardware.

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[libre-riscv-dev] [Bug 138] NLNet 2019 Coriolis2 Layout proposal 2019-10-029

[bugzilla-daemon]

http://bugs.libre-riscv.org/show_bug.cgi?id=138

--- Comment #10 from Luke Kenneth Casson Leighton <lkcl@lkcl.net> ---
# create tutorial / workflow page for setup, establish first layout
we need the alliance2/coriolis workflow documented, a suite of tutorials
found (or written), and a "test project" to be done which gives a guide
to completion time of layout.
https://libre-riscv.org/HDL_workflow/coriolis2/

URL: http://bugs.libre-riscv.org/show_bug.cgi?id=178
Budget: 3000

# layout for single-core 180nm ASIC
do layout for single-core 180nm ASIC including 1st level cache.
also peripherals: minimum priority is SDRAM 32 bit, 16550 UART, JTAG and SPI.
secondary priorities are 64 bit SDRAM, GPIO, PWM, EINT, QSPI, SDMMC, RGBTTL,
I2C and the pinmux.
package is to be QFP, maximum around 200 pins only including power and ground.

URL: http://bugs.libre-riscv.org/show_bug.cgi?id=199
Budget: 9000

* bug #200 - do layout for IEEE754 SIMD ALU 180nm
* bug #201 - coordinate and communicate modifications needed for nmigen
* bug #202 - modifications to HDL to suit coriolis2
* bug #203 - bugfixes and modifications to alliance/coriolis2
* bug #205 - Documentation for maintenance purposes of layout
* bug #204 - Transition support from symbolic to real layout and GDSII

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