* [libre-riscv-dev] [Bug 175] NLNet 2019 Wishbone proposal 2019-10-043
[not found] <bug-175-13@http.bugs.libre-riscv.org/>
@ 2020-03-13 14:53 ` bugzilla-daemon
0 siblings, 0 replies; 3+ messages in thread
From: bugzilla-daemon @ 2020-03-13 14:53 UTC (permalink / raw)
To: libre-riscv-dev
http://bugs.libre-riscv.org/show_bug.cgi?id=175
--- Comment #1 from Luke Kenneth Casson Leighton <lkcl@lkcl.net> ---
TODO fill out toplevel milestones for the Wishbone proposal,
ready for the MoU, add budgets for each milestone.
# Specfication Improvements
Improve the Wishbone B4 Specification to add streaming capability, comparable
to AXI4-Stream, and feed the improvements back into the current stewardship for
next Wishbone release.
Budget: 2.000 EUR
# Verification Models
Design Reference Implementations in nmigen and (System-)Verilog, Bus Function
Models and other functionality in SystemVerilog for verification with full unit
tests aiming best code coverage.
Budget: 6.230 EUR
# Reference Implementation / Demonstrator
Use some of the Libre RISC-V SoC peripherals as a test platform and
demonstrator (I2S Audio Streaming) for the proposed standard modifications.
Budget: 1.350 EUR
# Traveling Expenses
Traveling expenses for presenting the Wishbone improvements to the RISC-V
community once at the annual ORConf in 2020.
Budget: 650 EUR
# Special Outgoings
Budget for additional, unpredictable efforts - e.g. literature research or
other traveling expenses.
Estimated with 7 % of the whole sum.
Budget: 770 EUR
# Additional peripherals
Seek out existing (non-streaming) Wishbone Master
and Slave Bus implementations (or implement them if necessary), provide
formal proof unit tests of their correctness, and add additional example
peripherals.
Budget: 12500 EUR
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2020-03-13 14:53 ` [libre-riscv-dev] [Bug 175] NLNet 2019 Wishbone proposal 2019-10-043 bugzilla-daemon
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