[libre-riscv-dev] [Bug 241] New: OpenPOWER SImulation is needed of standards

[libre-riscv-dev] [Bug 241] New: OpenPOWER SImulation is needed of standards

[bugzilla-daemon]

http://bugs.libre-riscv.org/show_bug.cgi?id=241

            Bug ID: 241
           Summary: OpenPOWER SImulation is needed of standards
           Product: Libre Shakti M-Class
           Version: unspecified
          Hardware: PC
                OS: Linux
            Status: CONFIRMED
          Severity: enhancement
          Priority: ---
         Component: Source Code
          Assignee: lkcl@lkcl.net
          Reporter: lkcl@lkcl.net
                CC: libre-riscv-dev@lists.libre-riscv.org
   NLnet milestone: ---

Augmentation of an existing POWER ISA simulator that implements the proposed
standards is needed.  It is likely to start from gem5.

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[libre-riscv-dev] [Bug 241] OpenPOWER SImulation is needed of standards

[bugzilla-daemon]

http://bugs.libre-riscv.org/show_bug.cgi?id=241

--- Comment #1 from Luke Kenneth Casson Leighton <lkcl@lkcl.net> ---
*** Bug 256 has been marked as a duplicate of this bug. ***

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[libre-riscv-dev] [Bug 241] OpenPOWER SImulation is needed of standards

[bugzilla-daemon]

http://bugs.libre-riscv.org/show_bug.cgi?id=241

--- Comment #2 from Luke Kenneth Casson Leighton <lkcl@lkcl.net> ---
https://github.com/CSL-KU/SpectreGuard/blob/master/gem5/src/arch/power/isa/formats/integer.isa

this looks reasonable to work with.  it is a code-generator. so the hardware
for-loop will go in as c code outputted as a c for-loop.

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[libre-riscv-dev] [Bug 241] OpenPOWER SImulation is needed of standards

[bugzilla-daemon]

http://bugs.libre-riscv.org/show_bug.cgi?id=241

--- Comment #3 from Luke Kenneth Casson Leighton <lkcl@lkcl.net> ---
https://github.com/gem5-gpu

also interesting however possibly as an aside.  however texturisation and
shader functionality were added.

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[libre-riscv-dev] [Bug 241] OpenPOWER SImulation is needed of standards

[bugzilla-daemon]

http://bugs.libre-riscv.org/show_bug.cgi?id=241

--- Comment #4 from Luke Kenneth Casson Leighton <lkcl@lkcl.net> ---
https://github.com/cebix/macemu/blob/master/SheepShaver/src/emul_ppc/emul_ppc.cpp

another powerpc emulator

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[libre-riscv-dev] [Bug 241] OpenPOWER SImulation is needed of standards

[bugzilla-daemon]

http://bugs.libre-riscv.org/show_bug.cgi?id=241

--- Comment #5 from Luke Kenneth Casson Leighton <lkcl@lkcl.net> ---
http://pearpc.sourceforge.net/

another one to investigate

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[libre-riscv-dev] [Bug 241] OpenPOWER SImulation is needed of standards

[bugzilla-daemon]

http://bugs.libre-riscv.org/show_bug.cgi?id=241

--- Comment #6 from Luke Kenneth Casson Leighton <lkcl@lkcl.net> ---
(In reply to Luke Kenneth Casson Leighton from comment #5)
> http://pearpc.sourceforge.net/
> 
> another one to investigate

pear is, honestly, looking a lot simpler to work with, although it's going to
take some unit tests like those in riscv-isa-tests to get it into shape.

see
http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-March/005091.html

to get whatever we need into shape it will go like this:

* get "basic" (non-GUI) ability to run "bare-metal" programs.  this involves
either overloading a system call (writing one), peek/poke to a memory address
and having the emulator say "writes to this address are directed to stdout,
reads from this address result in characters from stdin being accepted".

* start writing some *really* simple unit tests (20-50 lines of assembler) that
test "addic", "mul", etc. etc.

* begin the process of allowing dynamic (runtime) emulation of 64-bit
instructions (not a static emulator-compile-time option)

* *recompile* the unit tests using a 64-bit ppc compiler and test that those
still work

* start adding "basic" SimpleV support (a 48-bit instruction with the 16-bit
"SV" Prefix) which does *NOT* support element-width.  just a straight for-loop
on integer math.

* write unit tests - in assembler - for SVPrefix add, addic, mul etc.

* move slowly forward adding full IEEE754 FP support (using Jacob's algorithmic
library, so that we have *proper* POWER IEEE754 emulation, not "x86" IEEE754
rules)

* add in elwidth support, predication, and so on, basically replicate the
traillazing done in the spike-sv emulator.


at the same time:

* add support for dynamic LE and BE (unit tests for the same)

* attempt to compile up more recent linux kernels, boot loaders (yaboot), in
particular track down why Debian 8.0 PPC ISO cannot recognise (find) yaboot
files on the ISO

* see if the MMU (TLB) code is adequate to run a 64-bit OS

* after the 64-bit bare-metal unit tests all pass, attempt to run larger
programs and even a linux kernel.


we *might* also want to consider porting the spike pk library to powerpc.  it's
a "bare minimum POSIX environment" which will allow the absolute bare minimum
of POSIX applications to function.  or, finding something else suitable to
port.

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[libre-riscv-dev] [Bug 241] OpenPOWER SImulation is needed of standards

[bugzilla-daemon]

http://bugs.libre-riscv.org/show_bug.cgi?id=241

cand@gmx.com changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |cand@gmx.com

--- Comment #7 from cand@gmx.com ---
https://github.com/lioncash/DolphinPPCTests
https://github.com/JustinCB/macemu/blob/master/SheepShaver/src/kpx_cpu/src/test/test-powerpc.cpp

Some Power unit test links.

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[libre-riscv-dev] [Bug 241] OpenPOWER SImulation is needed of standards

[bugzilla-daemon]

http://bugs.libre-riscv.org/show_bug.cgi?id=241

--- Comment #8 from Luke Kenneth Casson Leighton <lkcl@lkcl.net> ---
thanks to hugh, he pointed me in the direction of this:
https://github.com/power-gem5

it works however it leaks memory like a sieve

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