[libre-riscv-dev] [Bug 247] New: Implement AMDVLK / RADV Mesa Vulkan Driver

* [libre-riscv-dev] [Bug 247] New: Implement AMDVLK / RADV Mesa Vulkan Driver
@ 2020-03-13 15:09 bugzilla-daemon
  2020-03-13 18:12 ` [libre-riscv-dev] [Bug 247] " bugzilla-daemon
  0 siblings, 1 reply; 2+ messages in thread
From: bugzilla-daemon @ 2020-03-13 15:09 UTC (permalink / raw)
  To: libre-riscv-dev

http://bugs.libre-riscv.org/show_bug.cgi?id=247

            Bug ID: 247
           Summary: Implement AMDVLK / RADV Mesa Vulkan Driver
           Product: Libre Shakti M-Class
           Version: unspecified
          Hardware: PC
                OS: Linux
            Status: CONFIRMED
          Severity: enhancement
          Priority: ---
         Component: Milestones
          Assignee: lkcl@lkcl.net
          Reporter: addw@phcomp.co.uk
                CC: libre-riscv-dev@lists.libre-riscv.org
   NLnet milestone: ---
 total budget (EUR) 37500
  for completion of
       task and all
          subtasks:

An additional Vulkan driver is to be developed, alongside Kazan, starting
instead from preexisting code, AMDVLK or RADV. Decision still to be made.
AMDGPU assembly to be replaced with Libre RISCV SV Vectorisation and hardware
accelerated opcodes for Texture interpolation, YUV2RGB, Z buffering etc.

LLVM IR assembly portion extremely likely to be shared with Kazan.

first iteration

* 3 to 4 months software only (SwiftShader style) 3D MESA Driver, portable (x86
etc) using non-accelerated LLVM: EUR 12000
* 2 to 3 months adding iterated support for 3D opcodes to ISA Simulator (and
unit tests): EUR 7000
* 3 to 4 months first iterative effort developing and adding hardware
accelerated 3D opcodes to 3D MESA driver: EUR 12500
* 2nd iteration of opcodes in 3D MESA driver: EUR 12500
* Documentation to the level of an ISA Standards Proposal of all hardware
opcodes: 6000

Budget: 12000+7000+12500+6000=37500

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