[libre-riscv-dev] [Bug 249] New: Additional Wishbone B4 peripherals for Libre-SOC (including conversion from patented AXI4)

[libre-riscv-dev] [Bug 249] New: Additional Wishbone B4 peripherals for Libre-SOC (including conversion from patented AXI4)

[bugzilla-daemon]

http://bugs.libre-riscv.org/show_bug.cgi?id=249

            Bug ID: 249
           Summary: Additional Wishbone B4 peripherals for Libre-SOC
                    (including conversion from patented AXI4)
           Product: Libre Shakti M-Class
           Version: unspecified
          Hardware: PC
                OS: Linux
            Status: CONFIRMED
          Severity: enhancement
          Priority: ---
         Component: Source Code
          Assignee: lkcl@lkcl.net
          Reporter: lkcl@lkcl.net
                CC: libre-riscv-dev@lists.libre-riscv.org
   NLnet milestone: ---

Seek out existing (non-streaming) Wishbone Master
and Slave Bus implementations (or implement them if necessary, or convert from
AXI4 protocol), provide
formal proof unit tests of their correctness, and add additional example
peripherals.
See https://github.com/cocotb/cocotb/pull/439 in particular

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